PLC Reset Coil: RESET, OTU, RS Logic & Examples
Quick answer
A PLC reset coil writes FALSE to a stored Boolean when its rung is true. It normally clears a bit previously set by a SET coil, Rockwell OTL or an RS/SR latch. When the reset rung is false, the reset instruction leaves the bit unchanged.
Key Takeaways
- A PLC reset coil writes FALSE to a stored Boolean when its rung is true. It normally clears a bit previously set by a SE...
- Beginner-level topic in Ladder Logic Elements
- Commonly used in: Clearing a completed sequence or request bit, Acknowledging a non-safety latched alarm after its cause has cleared
Detailed Definition
A reset coil is a state-clearing instruction, not the inverse of a standard output coil. A normal coil writes the rung result on every execution. A reset coil writes FALSE only while its reset condition is true; otherwise it makes no change. The corresponding set instruction is therefore what first makes the stored bit TRUE.
The order and dominance of writes matter. Separate SET and RESET rungs usually resolve according to execution order when both are true, while an RS or SR function block defines which input wins. A software reset also must not be confused with a safety reset: resetting an internal command does not prove that field energy has been removed or that a safety function is ready to restart.
Evidence and scope
Reset behavior was checked against current Rockwell Logix Designer, Siemens STEP 7 and CODESYS documentation. The page describes ordinary program-state logic, not a certified safety reset. Restart, retentivity and output behavior still require a controller-specific test.
Technical review:
Critical behavior
- A true reset condition writes FALSE; a false reset condition normally leaves the addressed bit unchanged.
- A reset coil needs a defined owner and corresponding set path. Search the complete project for every write to the same bit.
- Separate set and reset rungs can become order dependent. An RS/SR block makes simultaneous-input priority explicit.
- Retentive instruction behavior during normal scans does not by itself define power-cycle, download or first-scan behavior.
- Do not use an ordinary reset coil as evidence of a safety reset or safe torque removal.
Verification checklist
- 1Cross-reference every instruction or assignment that can write the stored bit.
- 2Test set only, reset only, neither input and both inputs together.
- 3Confirm cold start, warm restart, download and routine-not-scanned behavior.
- 4Verify the physical command and feedback separately from the internal request bit.
- 5Document whether reset or set must dominate and encode that priority explicitly.
IEC and vendor terminology
Similar-looking instructions do not always have identical execution, initialization or storage behavior.
| Platform | Common term | What to verify |
|---|---|---|
| IEC-style Ladder Diagram | Reset coil / R coil | When enabled, writes FALSE to the Boolean. A matching set instruction writes TRUE. Exact glyphs and restart behavior are implementation specific. |
| Rockwell Studio 5000 | OTU | When rung-condition-in is true, Output Unlatch clears the BOOL. A false rung does not change the bit; OTL is the usual paired set instruction. |
| Siemens STEP 7 | R coil; RS / SR | R clears an addressed bit. Siemens documents different simultaneous-input priority for its RS and SR bistables, so confirm which block is selected. |
| CODESYS Standard library | RS | The documented RS block is reset dominant: RESET1 wins when SET and RESET1 are both TRUE. |
Reset-dominant stored run request
|----[ Start_Request ]------------------------(S) Run_Request----|
|----+----[ Stop_Request ]--------------------(R) Run_Request----|
| +----[ Process_Fault ]--------------------------------------|
|----[ Run_Request ]----[ Permissives_OK ]----( ) Motor_Command--|Reset-coil state and priority table
This table uses reset-dominant behavior. If separate set and reset instructions are used instead, confirm program order on the target controller.
| State / phase | Set request | Reset request | Stored result |
|---|---|---|---|
| Hold | FALSE | FALSE | Previous state |
| Set | TRUE | FALSE | TRUE |
| Reset | FALSE | TRUE | FALSE |
| Both asserted | TRUE | TRUE | FALSE for reset-dominant RS |
Working LD and ST example
Reset a stored cycle request without bypassing permissives
Use reset-dominant state for a non-safety cycle request, then calculate the equipment command separately.
Ladder Diagram
|----[ Start_Pulse ]------------------------(S) Cycle_Request----|
|----+----[ Stop_Pulse ]--------------------(R) Cycle_Request----|
| +----[ Process_Fault ]--------------------------------------|
|----[ Cycle_Request ]----[ Permissives_OK ]----( ) Run_Command-|Structured Text
IF StopPulse OR ProcessFault THEN
CycleRequest := FALSE; // reset wins
ELSIF StartPulse THEN
CycleRequest := TRUE;
END_IF;
RunCommand := CycleRequest AND PermissivesOK;Expected result: A simultaneous start and stop leaves CycleRequest FALSE. Losing a permissive removes RunCommand even if the stored request remains TRUE.
Failure modes and diagnostic checks
| Symptom | Likely cause | Check next |
|---|---|---|
| The bit turns on again immediately after reset | A later OTL, SET, assignment or mapped write sets the same tag in the same execution. | Cross-reference every write and record execution order, task and routine conditions. |
| Reset works online but not after a restart | The stored variable or surrounding state has different cold-start or retentive behavior. | Run documented cold, warm, download and first-scan tests on the target controller. |
| A maintained reset prevents the next start | The reset signal remains TRUE or reset is dominant by design. | Trend SetRequest, ResetRequest and the stored bit; require reset release before accepting a new start. |
| The internal bit is false but the device remains energized | The physical output is forced, written elsewhere, mapped differently or held by external circuitry. | Inspect the output tag, module state, forces, wiring and field feedback independently. |
Current primary and technical sources
These sources support the behavior summarized on this page. The project's controller, firmware and IDE help remain authoritative for implementation.
- Output Unlatch (OTU), Logix Designer V38
Rockwell Automation — BOOL clearing behavior and overwritten-operand warning
- Set and reset instructions
Siemens — S/R coils and RS/SR simultaneous-input priority
- RS bistable function block
CODESYS — Reset-dominant Standard-library equation and interface
- IEC 61131-3:2025 publication record
IEC — Current programmable-controller language standard record
Continue with the practical guide
Common Questions
What is Reset Coil?
A PLC reset coil writes FALSE to a stored Boolean when its rung is true. It normally clears a bit previously set by a SET coil, Rockwell OTL or an RS/SR latch. When the reset rung is false, the reset instruction leaves the bit unchanged.
When should I use Reset Coil?
Reset Coil is particularly useful in scenarios such as Clearing a completed sequence or request bit and Acknowledging a non-safety latched alarm after its cause has cleared. Consider implementing it when you need reliable, efficient solutions for these types of applications.
What should I verify before using Reset Coil?
Cross-reference every instruction or assignment that can write the stored bit. Test set only, reset only, neither input and both inputs together. Confirm cold start, warm restart, download and routine-not-scanned behavior. Verify the physical command and feedback separately from the internal request bit. Document whether reset or set must dominate and encode that priority explicitly.
What are related concepts I should learn?
To fully understand Reset Coil, you should also familiarize yourself with TON (Timer On-Delay), TOF (Timer Off-Delay), and CTU (Count Up). These concepts work together in industrial automation systems.
Continue Learning
Ready to deepen your understanding of Reset Coil? Here are some recommended resources:
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