Ladder Logic Elements

Current count in timer or counter showing progress toward preset.

Instruction that always evaluates false, used to disable rungs during testing.

Shifts bits in array one position left, loading new bit at right end.

Shifts bits in array one position right, loading new bit at left end.

Execution order of parallel branches in ladder logic affecting scan sequence.

A ladder logic symbol representing an output that energizes when power flows through the rung, controlling physical outputs or internal memory bits.

Logic operations comparing two values (EQU, NEQ, LES, GRT, LEQ, GEQ).

Parameter in array instructions defining number of elements to process.

Current index pointer in array operations like shift registers and sequencers.

Counter that decrements from preset value toward zero with each input pulse.

A counter that increments its accumulated value each time the input transitions from false to true, used for counting parts, cycles, or events.

Bidirectional counter with separate count up and count down inputs.

Status bit that turns on when timer reaches preset or counter reaches target.

Status bit indicating instruction input is true and instruction is active.

Instruction marking end of main program execution in scan cycle.

Comparison contact that passes power when two values are equal.

A trigger that activates for one scan cycle when an input transitions from true (1) to false (0), detecting when signals turn off.

First-In-First-Out stack instruction that loads data into queue.

Removes oldest data from FIFO queue when triggered.

Copies multiple consecutive elements from source to destination array.

Fills destination array with copies of single source value.

Iterative control structure executing code block specified number of times.

List of I/O points with forced values overriding program logic.

Comparison contact true when first value is greater than second value.

Comparison contact true when first value is greater than or equal to second.

Reads physical input immediately instead of waiting for input scan phase.

Updates physical output immediately instead of waiting for output scan phase.

Program flow instruction that skips to labeled location when condition is true.

Jump to Subroutine (JSR) is an Allen-Bradley ladder logic instruction that calls another routine, executes its code, and returns to continue the calling rung. Used to organise PLC programs into reusable, manageable blocks.

Target destination marker for jump instructions in ladder logic programs.

Output that remains energized after input goes false, requiring separate unlatch command to reset.

Comparison contact true when first value is less than second value.

Comparison contact true when first value is less than or equal to second.

Last-In-First-Out stack instruction that pushes data onto stack.

Pops most recent data from LIFO stack when triggered.

Tests if value is within or outside specified range defined by low and high limits.

Compares specific bits of two values using mask to ignore certain bits.

Copies only bits specified by mask from source to destination.

Master Control Relay (MCR) is a ladder logic zone-control instruction that disables all non-retentive outputs within its zone when the MCR rung is false. Used to implement emergency-stop zones and operating-mode gating without rewriting individual rungs.

Function block performing arithmetic operations within ladder logic.

Copies data from source location to destination when rung is true.

Branch within a branch creating complex conditional logic structures.

NOP (No Operation) is a placeholder PLC instruction that performs no action when the program scans it. Programmers use it to reserve a rung for future logic, temporarily disable code without deleting it, or pad program timing — it consumes one scan step but changes no data, bits, or outputs.

A contact symbol in ladder logic that allows power flow when the associated bit is false (0), representing an open switch when energized.

A contact symbol in ladder logic that allows power flow when the associated bit is true (1), representing a closed switch when energized.

Comparison contact that passes power when two values are different.

Instruction that passes power for exactly one scan when input transitions from false to true.

Allen-Bradley standard output coil, energized when rung is true.

Allen-Bradley latch output that stays on after input goes false.

Allen-Bradley unlatch instruction that turns off latched outputs.

Status bit set when counter or math operation exceeds maximum value.

Ladder logic structure providing alternate paths for power flow (OR logic).

Virtual electrical current path through ladder logic from left to right rail.

Vertical lines in ladder diagram representing power source (left) and return (right).

Target value for timers and counters defining when done bit activates.

Timer generating fixed-duration output pulse regardless of input duration.

Resets output to false when rung is true, clearing set coils or other outputs.

Output that maintains state through power cycle using battery backup.

Exits subroutine and returns control to calling program at next instruction.

A trigger that activates for one scan cycle when an input transitions from false (0) to true (1), used for detecting button presses and signal changes.

Timer that retains accumulated value when input goes false, resuming from where it stopped.

Descriptive text explaining the purpose and operation of a ladder logic rung.

Diagnostic counter tracking number of PLC scan cycles for performance monitoring.

Sequential execution of rungs from top to bottom affecting logic results.

Compares input pattern with stored patterns for sequence verification.

Captures current input pattern into sequencer array position.

Steps through array of output patterns for sequential machine control.

Sets output to true when rung is true, output remains true until reset by another instruction.

Instruction invoking separate code section with optional parameters.

Status bit true while timer is actively counting but hasn't reached preset.

Debugging instruction that ends program execution at specific point.

A timer that keeps output active for specified duration after input turns off, used for delayed shutdowns and cooling cycles.

A timer that waits for a specified duration after being enabled before activating its output, commonly used for delayed start operations.

Special contact detecting change of state in Sequential Function Charts.

Status bit set when counter goes below zero or math result is too small.

Output that resets a latched coil, turning it off regardless of latch input state.

Allen-Bradley normally open contact instruction, true when bit is 1.

Allen-Bradley normally closed contact instruction, true when bit is 0.