Bistables & Edge DetectionBeginnerIEC 61131-3

F_TRIG Falling Edge: PLC Timing and Examples

F_TRIG detects a Boolean transition from TRUE to FALSE. It compares CLK with stored previous state and makes Q TRUE for one execution of the task or block call. If CLK remains FALSE, Q returns FALSE on the next call. The instance must retain its own edge memory and execute regularly.

The F_TRIG (Falling Edge Trigger) function block detects a TRUE-to-FALSE transition on its input (CLK). The output (Q) is TRUE for exactly one PLC scan cycle when the falling edge occurs. F_TRIG is the complement of R_TRIG and is used when actions need to be triggered on signal de-activation, such as detecting when a button is released, when a sensor loses its target, or when a process condition ends.

Parameters

Inputs

Name	Type	Description
CLK	BOOL	Input signal to monitor for falling edge

Outputs

Name	Type	Description
Q	BOOL	TRUE for one scan on falling edge of CLK

How F_TRIG falling-edge detector works scan by scan

Read the waveforms and state table together. The diagram shows the sequence; the table states what the program should observe at each execution.

F_TRIG falling-edge timing diagram

CLK begins high, then falls twice. Q is true for one block execution at each high-to-low transition and remains false while CLK is steadily high or low.

Blue is the input, green is the boolean output, and amber is elapsed time or current count. Transitions are shown at task executions; real timing resolution depends on the controller and task.

State table

Moment	Input	Internal state	Output	Engineering meaning
Previously high	CLK = TRUE	Previous = TRUE	Q = FALSE	The detector is armed to recognize the next transition to FALSE.
Falling edge	CLK changes TRUE → FALSE	Previous updates to FALSE	Q = TRUE for this call	Execute the event action once during this task or block execution.
Held low	CLK remains FALSE	Previous = FALSE	Q = FALSE	A state is not repeatedly treated as an edge.
Returns high	CLK changes FALSE → TRUE	Previous updates to TRUE	Q = FALSE	The detector re-arms; this is a rising edge, not an F_TRIG event.

Ladder and Structured Text examples

Count a part when the trailing edge leaves a sensor

|----[ Part_Sensor ]----[ F_TRIG PartLeaves ]----|
|----[ PartLeaves.Q ]----[ CTU CompletedParts ]----|
|                         PV: 20                 |

Use one persistent PartLeaves instance. This counts the sensor’s TRUE-to-FALSE transition once; it does not debounce the sensor or recover a pulse that the input/task path never sampled.

IEC-style F_TRIG instance call

VAR
    PartLeaves     : F_TRIG;
    PartSensor     : BOOL;
    CompletedParts : DINT;
END_VAR

PartLeaves(CLK := PartSensor);

IF PartLeaves.Q THEN
    CompletedParts := CompletedParts + 1;
END_IF;

Call the same persistent instance once per intended cycle. A temporary instance, shared instance or conditionally skipped call can destroy the previous-state history needed for correct edge detection.

Vendor compatibility

A shared mnemonic does not guarantee an identical interface or state machine. Confirm the instruction help for the controller, firmware, language and library version used on the project.

Platform	Instruction	What maps cleanly	Caveat to verify
CODESYS Standard library	F_TRIG	CLK falling from TRUE to FALSE produces a one-call Q pulse	Library version, instance lifetime and task call determine initialization and observation of the pulse.
Siemens S7-1200/1500	F_TRIG	Compares current CLK with previous state stored in the instance and sets Q for one cycle	Siemens documents a startup boundary tied to instance initialization. Test cold and warm starts with the selected CPU and DB settings.
Rockwell Logix	OSF in Ladder; OSFI in FBD/ST	Produces a one-scan output on a true-to-false rung or input transition	Storage/output operands and prescan behavior are Logix-specific; do not substitute IEC instance assumptions.

Failure modes and edge cases to test

CLK is already FALSE at startup

Initialization determines whether a first-cycle pulse is possible. Do not use an assumed startup edge; test and explicitly initialize the instance/state.

Input pulse is shorter than the sampling path

F_TRIG cannot detect a high state the input module and task never observed. Use hardware capture, a faster task or pulse stretching.

The block call is skipped while CLK changes

Stored previous state becomes stale. A pulse can be delayed, missed or created when execution resumes.

One instance is reused for two signals

The signals overwrite one previous-state memory. Give every independent signal its own instance.

A bouncing contact falls repeatedly

Each sampled falling edge can produce a pulse. Edge detection is not debounce filtering.

Verification checklist

1Trend CLK, Q and the consuming event at task resolution.
2Test steady FALSE, steady TRUE, one falling edge and repeated bounce.
3Test the shortest credible field pulse against input and task update rates.
4Test cold start, warm restart and disabled-routine behavior.
5Confirm one persistent instance per signal and one call per intended execution.

Current primary and technical sources

These sources support the behavior summarized here. The exact controller, firmware, instruction and installed-library help remain authoritative for implementation.

F_TRIG, Standard library
CODESYS — Current function-block reference
F_TRIG: Detect negative signal edge, STEP 7 V21
Siemens — One-cycle behavior, instance state and CPU-startup note
Bit Instructions, Logix Designer V38
Rockwell Automation — OSF and OSFI falling-edge alternatives
IEC 61131-3:2025 publication record
IEC — Current programmable-controller language standard record

Continue with the practical guide

R_TRIG rising edgeCompare false-to-true detection and one-execution timing PLC one-shot guidePlace edge detection in the scan and task model PLC scan cycleUnderstand missed pulses and task-resolution limits

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Platform-Specific Implementation

Siemens (TIA Portal)

Use F_TRIG instruction or N (negative edge) contact in TIA Portal.

Allen-Bradley (Studio 5000)

Use OSF (One-Shot Falling) instruction in Studio 5000.

CODESYS

Standard F_TRIG in Standard library.

Common Applications

Button release detection
Sensor target lost event
Process completion trigger
Falling edge counting
De-energize event logging

Common Mistakes to Avoid

Confusing with R_TRIG behavior
Not using separate instances for each signal

Frequently Asked Questions

What is F_TRIG (Falling Edge Detection) in PLC programming?

Detects TRUE-to-FALSE transition, outputs single-scan pulse on falling edge. The F_TRIG (Falling Edge Trigger) function block detects a TRUE-to-FALSE transition on its input (CLK). The output (Q) is TRUE for exactly one PLC scan cycle when the falling edge occurs.

What are common applications of F_TRIG (Falling Edge Detection)?

F_TRIG (Falling Edge Detection) is commonly used for: Button release detection, Sensor target lost event, Process completion trigger, Falling edge counting, De-energize event logging.

How do I use F_TRIG (Falling Edge Detection) in different PLC platforms?

Siemens: Use F_TRIG instruction or N (negative edge) contact in TIA Portal. Allen-Bradley: Use OSF (One-Shot Falling) instruction in Studio 5000. CODESYS: Standard F_TRIG in Standard library.