SET / RESET PLC LADDER — SYMBOLIC TEACHING OUTLINE
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Purpose
  Demonstrate one-writer, reset-dominant Boolean memory.
  This is deliberately vendor-neutral and is NOT an importable PLC project.

Inputs / derived requests
  StartPulse       := qualified rising-edge request to set state
  StopRequest      := qualified level request to clear state
  ModeNotAllowed   := ordinary-control reason to clear state
  FirstScanClear   := project-approved startup clear request

Internal state
  RunMemory        := accepted ordinary run request; never a safety output

Derived requests
  SetReq   := StartPulse
  ResetReq := StopRequest OR ModeNotAllowed OR FirstScanClear

Reset-dominant next-state equation
  RunMemory_Next := (RunMemory OR SetReq) AND NOT ResetReq

Equivalent explicit decision
  IF ResetReq THEN
      RunMemory_Next := FALSE;
  ELSIF SetReq THEN
      RunMemory_Next := TRUE;
  ELSE
      RunMemory_Next := RunMemory;
  END_IF;

Exactly one write
  RunMemory := RunMemory_Next;

Separate command/output layer
  RunCmd := RunMemory AND AutoMode AND ProcessPermits AND NOT OrdinaryFault;
  PhysicalOutput := RunCmd;  // map only in the approved I/O owner

Required project decisions
  - Exact PLC/CPU, firmware, editor and language/dialect
  - Set/Reset instruction or equation semantics
  - Simultaneous-command priority
  - Input capture and edge-detection behavior
  - One task/routine owner and execution schedule
  - Cold/warm restart, power loss, download and mode-change behavior
  - Retentive/non-retentive memory configuration
  - HMI/remote command handshake
  - Feedback timeout and fault lifecycle
  - Safety-system boundary and independent validation

Minimum tests
  Run SR-01 through SR-20 from the companion acceptance matrix on the
  exact target and retain synchronized request/state/command/feedback traces.